Pick a biasing topology, set the parts, and read the operating point off the schematic. The load line shows where the transistor is sitting; the signal view shows what actually comes out the other side.
Supply & device
Components
Enter values as 47k, 2.2M,
100n, 4u7 or plain ohms.
Schematic
Output at collector — before C3
Output after C3 — AC-coupled
Frequency response
Node voltages
Branch currents
Small signal (AC)
Swing & power
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DC model: β-model with the base network solved exactly, then clamped at VCE(sat) so a saturated stage reports what a real device does rather than an impossible negative collector voltage. VBE is 0.3 V for germanium and 0.7 V for silicon; VCE(sat) 0.1 V and 0.2 V. The signal view shows the AC-coupled OUT node, so the trace is centred on 0 V \u2014 the collector's DC level lives on the schematic. It is a mid-band linear model with hard clipping at the AC load line limits: gain, phase inversion, clipping asymmetry and coupling-capacitor rolloff (C1 and C3) are shown, but not device curvature, so the soft onset of real transistor distortion is not modelled. No junction capacitance either, so there is no HF rolloff.
